FIFO memory systems are used in a wide variety of applications, such as buffering high-speed serial data immediately after it has been parallelized, for temporary storage of a data packet during packet processing, or buffering data going to or coming from a disk. Data values that are sequentially written to a FIFO buffer are read from the FIFO buffer in the same order, namely the first data entered into the FIFO memory system is the first data read from the FIFO memory system.
FIFO buffers are implemented in RAM and the flow of data into and out of RAM is controlled by address counters that track the read and write addresses being used. The address counters coordinate the data flow into and out of RAM to insure that memory is available to accept incoming data to prevent overflowing the RAM, and that data is stored in RAM before a read operation executes.
Several status flags are available in FIFO memory systems, such as FIFO FULL and FIFO EMPTY, which indicates the RAM is either full or empty, which indicate that there is sufficient space in RAM for a WRITE to occur or sufficient data in RAM for a READ to be performed. For example, if a WRITE function is to be enabled, the FIFO FULL status flag will indicate whether the data can be written into memory. If a read is to be performed, the FIFO EMPTY status flag will indicate whether there is any data available in the FIFO.
FIFO memory systems can be synchronous or asynchronous. A FIFO memory system in which both the read address counter and the write address counter are clocked by the same clock signal is referred to as a synchronous FIFO memory system. In contrast, a FIFO memory system in which the read address counter and the write address counter are clocked by different clock signals is referred to as an asynchronous FIFO memory system. Asynchronous FIFO memory systems are extremely useful in digital data systems where different sides of the FIFO memory system are independently clocked, either at different clock rates, or at the same clock rate, but with a phase difference (“skew”).
In both synchronous and asynchronous FIFO systems, the read and write address counters are circular counters that wrap around to an initial address after the last address is accessed. The read and write address counter output signals are either multiplexed to address a single-port random access memory (RAM), or they are separately provided to address different input ports of a multi-port RAM (e.g. a dual-port RAM).
FIFO memory systems have been implemented in programmable logic devices (“PLDs”), such as a field-programmable gate arrays (“FPGAs”) and complex programmable logic devices (“CPLDs”). PLDs are semiconductor integrated circuits that have a “fabric” of programmable logic, and other functional portions, such as RAM.
FIFO memory systems have been implemented in PLDs using the fabric of the PLD to provide the FIFO control logic, such as generating the status flags, and providing the write and read addresses of FIFO memory systems. Such FIFO memory systems are described in co-owned U.S. Pat. Nos. 5,898,893 and 6,434,642, the disclosures of which are hereby incorporated in their entirety for all purposes. The logic for operating the FIFO memory system is typically developed in configurable logic blocks (“CLBs”) surrounding an embedded block of RAM (“BRAM”), and the embedded BRAM is operated as a FIFO buffer. In alternative designs, distributed memory is used in a FIFO memory system. However, in either instance it is often desirable to have CLBs available to perform other logic functions. Additional information regarding configuring FIFO memory systems in FPGAs is available in Application Note XAPP131, available from Xilinx, Inc., of San Jose, Calif.
Programming a CLB to provide the logic functions of a FIFO memory system can be challenging in certain applications, particularly generating status flags in asynchronous applications. Incorrect user programming can result in unreliable operation of the FIFO memory system. Another aspect of implementing the logic in CLBs is that the operating speed of the CLB is typically less than the operating speed of the memory, which limits the maximum speed that the FIFO memory system can operate.
Therefore, it is desirable to provide a PLD with higher operating speed and more reliable operation.